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Entwicklung und Implementierung verschiedener Signalextraktionstechniken für FPGA-basierte Systeme

Development and Implementation of Advanced Signal Extraction Techniques for FPGA-based Systems

General Setting

At iMEK, within the context of the Collaborative Research Center CRC1615, a 3D EIT system with a high number of electrodes is being developed. Due to the high number of electrodes (up to 256), numerous measurements are necessary for each image reconstruction. To conduct these in a satisfactory time, measurements must be parallelized. A microcontroller is no longer sufficient for controlling the complex EIT measurement hardware and reading the parallel analog-to-digital converters (ADC); thus, an FPGA should be used instead. In order to achieve optimal reconstruction results we require an accurate noise resilient extraction of phase and amplitude of a measurement.

Task Description:

Objective:

The primary goal of this project is to simulate, analyze, and implement various methods for phase and amplitude extraction in signal processing applications. We aim to integrate these methods into an existing measurement chain effectively. Special attention will be given to enhancing performance through the use of a Lock-In Amplifier and exploring potential machine learning approaches.

Key Tasks:

1. Simulation of Phase and Amplitude Extraction Methods:

   • Assemble different techniques for amplitude and phase extraction for EIT.

     • Potential exploration of Machine Learning Approaches:

       • Investigate the application of machine learning techniques for phase and amplitude extraction.

       • Assess the viability and effectiveness of machine learning in enhancing extraction processes compared to traditional methods.

     • Mandatory in-Depth Analysis of the Lock-In Amplifier:

       • Carry out a comprehensive study of the Lock-In Amplifier's capabilities and limitations.

       • Identify scenarios where the Lock-In Amplifier is indispensable for phase and amplitude extraction.

   • Conduct detailed simulations of different techniques for phase and amplitude extraction, focusing on their effectiveness at specific frequencies.

   • Evaluate the potential performance and arising benefits of the different methods.

2. FPGA Implementation:

   • Select the three most promising methods (including at least one that utilizes the Lock-In Amplifier) for implementation.

   • Develop and integrate these methods on an FPGA platform, ensuring seamless operation within the existing measurement chain.

3. Integration and Testing:

   • Incorporate the implemented solutions into the predefined measurement chain.

   • Test the entire system for accuracy, efficiency, and reliability in extracting phase and amplitude information.

Sketch of the Measurement Chain

Deliverables:

• A report detailing the simulation results and comparative analysis of the methods studied.

• A comprehensive evaluation of the Lock-In Amplifier's performance.

• Documentation and source code for the FPGA implementations of the selected methods.

• An integrated and tested measurement chain capable of enhanced phase and amplitude extraction.

Zeitplanung:

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