PA - Design and Implementation of an Architecture for FPGA-Based High-Speed Data Transfer for Real-Time Image Reconstruction in a 3D EIT System

Entwicklung einer Architektur für FPGA-basierte Hochgeschwindigkeits-Datenübertragung und maschinelles Lernen zur Echtzeit-Bildrekonstruktion in einem 3D-EIT-System

Design and Implementation of an Architecture for FPGA-Based High-Speed Data Transfer and Machine Learning for Real-Time Image Reconstruction in a 3D EIT System

General Setting

At iMEK, within the context of the Collaborative Research Center CRC1615, a 3D EIT system with a high number of electrodes is being developed. Due to the high number of electrodes (up to 256), numerous measurements are necessary for each image reconstruction. To conduct these in a satisfactory time, measurements must be parallelized. A microcontroller is no longer sufficient for controlling the complex EIT measurement hardware and reading the parallel analog-to-digital converters (ADC); thus, an FPGA should be used instead.

Task Description

With the advancing development of 3D EIT (Electrical Impedance Tomography) systems that use a high number of electrodes, the complexity and scale of the required data processing also increase. The goal of this work is to implement an efficient architecture for capturing, processing, and transmitting measurement data from an EIT system that uses up to 256 electrodes. The data should be directly transferred from an FPGA with a transmission speed of 10 Gbit/s over Ethernet to a PC, where machine learning software is used for real-time display of the reconstructed images.

Implemented Foundations

• An FPGA architecture has been developed and successfully implemented, enabling parallel measurements of the electrodes in an EIT system. This architecture includes the following key features:

• Control and read capabilities for multiple ADCs (16-bit, 2 MSPS, SPI Bus) have been fully established.

• Digital filtering processes have been implemented to significantly improve the quality of the signals.

• Complex FFTs are utilized to evaluate both the amplitude and phase of the measurement signals, enhancing the system's analytical capabilities.

Project Objectives

Implementation of a High-Speed Data Transmission Path

• Utilize a Xilinx Zynq UltraScale+ XCZU7EV for data transfer with a rate of 10 Gbit/s over Ethernet.

• Ensure continuous data flow to a PC-based analysis environment.

Development of a PC-Based Program for Control and Data Processing

• Implement communication with the FPGA via Ethernet.

• Enable live rendering of image reconstructions using GPU-based processing with a linear one-step solver.

Evaluation and Optimization of the System

• Evaluate latency, data throughput, and resource utilization.

• Define interfaces and physical connections between the FPGA and measurement hardware.

• Investigate the feasibility of conducting 256 fully parallel measurements within a 100 ms per measurement cycle.

Integration of Design Verification

To enhance the high-speed data path design, integrate Design Verification into the project:

• Verify the implemented protocol using a Layered Testbench Architecture to improve design correctness and robustness.

• Use constrained random testing to generate diverse input scenarios, ensuring broader functional coverage of the design.

• Aim to achieve maximum possible functional coverage for thorough design validation.

Methodology

• Design and synthesis of FPGA logic using the Vivado Design Suite to implement the necessary algorithms and data paths.

• Development of PC-based software components for machine learning processing.

• Implementation of a web-based GUI using modern web technologies for visualized control and display of reconstructed images.

Expected Outcomes

The successful implementation of this work should demonstrate that an FPGA-based architecture enables real-time processing and transmission of large data volumes. By integrating machine learning, the reconstructed images should be verified and optimized in real-time, significantly enhancing image quality and the applicability of EIT within the scope of CRC1615.

Checklist

• Introduction / tour in M4

• Urheberrechtsvereinbarung signed

• if applicable: signed confidential agreement

• official registration

Helpful links:

• Thesis Work / Studentische Arbeiten 

• Criteria for the evaluation of Bachelor's and Master's theses, handout version

• Laborordnung

• Spotlights / Kurzvorträge

• Templates (Latex, ppt etc.)

Document Upload Final Thesis / Dokumentenabgabe Abschlussdokument

• Handed in as Gitlab Wiki

• Wiki and Code are copied to “T/50_Projekte/SFB1615_Smart_Reactors/A02/80_Students/Lagidi_PA_FPGA_GPU”

• Gitlab-Repository https://collaborating.tuhh.de/m-4/sfb1615-imek/sfb1615-eit/fpga-gpu-connection

File of final presentation / Dokumentenabgabe Abschlusspräsentation

Open

Link for further files / Link für weitere Dokumente