MA - FPGA-Based Master-Slave Control for a Highly Parallel EIT Measurement System
FPGA-Based Master-Slave Control for a Highly Parallel EIT Measurement System
Task Description / Aufgabenstellung
Topic
At iMEK, within the context of the Collaborative Research Center CRC1615, a 3D EIT system with a high number of electrodes is being developed. Due to the high number of electrodes (up to 256), numerous measurements are necessary for each image reconstruction. To conduct these in a satisfactory time, measurements must be parallelized. A microcontroller is no longer sufficient for controlling the complex EIT measurement hardware and reading the parallel analog-to-digital converters (ADC); thus, an FPGA should be used instead.
Master's Thesis Description and Tasks
Goal of the Master's Thesis
The goal of this Master's Thesis is to build the Master Module and a Master-Slave Architecture for a Modular EIT System (Electrical Impedance Tomography).
Each Slave Module uses a Zynq-7000 FPGA.
These Slave Modules must be controlled in parallel to acquire and measure data.
It is particularly important to be able to match the data to the corresponding module.
To achieve this, you need to:
Implement the Master Module.
Adjust the implementation of the Slave Modules accordingly.
The data transfer is planned via Ethernet.
Current Challenges / Tasks
The following challenges must be solved within the scope of the thesis:
The communication between the modules
Storing the data according to the measurement plan.
Loading arbitrary waveforms onto the FPGAs.
Adjusting the data extraction method accordingly.
Defining a well-documented API for control.
Building a User Interface (UI) for data acquisition.
Analyzing the collected data in detail.
Taking measurements.
Performing reconstructions from the measured data to validate your work.
Potential Future Work
A potential area of work is focusing on the time domain on the FPGA, so that reconstruction is not only based on the Fourier Transform but potentially also directly in the time domain.
This would result in a working system and explore the pre-processing on the FPGA.
Building on Existing Work
You can build on the following existing work:
An existing data transfer mechanism.
Potentially working ADC and DAC modules for the slave.
An existing Master's Thesis that explores different implementation methods for Phase-Amplitude-Extraction.
The currently running Project Work on compressed Sensing, from which you can extract information.
Name: | @Sai Bhavani |
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Thesis Type MA/BA/PA: | MA |
Student ID / Matrikelnummer: |
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Field of Study / Studiengang: |
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Official start-date / Offizieller Beginn: |
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Final-report-due /Abgabe: |
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Spotlight-presentations: | 1. 2. 3. |
Zweitprüfer / Second Examiner | @Moritz Hollenberg (Betreuer)
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Confidential / Vertraulich | no |
Zeitplanung:
Checklist
Introduction / tour in M4
Urheberrechtsvereinbarung signed
if applicable: signed confidential agreement
official registration
Helpful links:
Document Upload Final Thesis / Dokumentenabgabe Abschlussdokument
File of final presentation / Dokumentenabgabe Abschlusspräsentation
Link for further files / Link für weitere Dokumente