PA - Systementwurf einer modularen FPGA-Architektur für Elektrische Impedanztomographie

PA - Systementwurf einer modularen FPGA-Architektur für Elektrische Impedanztomographie

Systementwurf einer modularen FPGA-Architektur für Elektrische Impedanztomographie

 

System Engineering of a Modular FPGA-Based Data Processing Architecture for Electrical Impedance Tomography (EIT)

 

Objective:

Deliver a parametric and modular solution for configuring an FPGA-based data acquisition and processing system for EIT. The tool allows users to input system design parameters and receive an automatically derived, constraint-compliant system configuration — from hardware modules to protocols and memory layout.

Deliverables Overview


1. Modularization of System Architecture

Goal: Define a flexible and scalable system structure that supports a hierarchy of components.

Subtasks:

  • Partitioning of system responsibilities across a Main FPGA and multiple Slave FPGAs

  • Modular definition of:

    • Stimulation units

    • Data acquisition channels

    • Communication interfaces

    • Processing pipelines

  • Interface abstractions for arising communication

  • Hierarchical control and synchronization structure

 


2. Parametrization Framework

Goal: Formalize all design-critical variables and their interdependencies.

Subtasks:

  • Define input parameters:

    • Number of electrodes/modules

    • ADC/DAC resolution and sampling rate

    • Interface protocol options

    • Power, logic, and throughput constraints

    • Processing stages to be handled on FPGA vs. PC

  • Construct dependency models:

    • Bitrate as function of ADC/sample rate/module count

    • RAM usage vs. number of buffers and sampling windows

    • Latency models based on data paths

  • Build validation logic:

    • Resource feasibility

    • Bandwidth and timing compliance

 


3. Optional Frontend Interface

Goal: Provide a software interface to enter parameters, enforce constraints, and return valid system configurations.

Subtasks:

  • Design GUI and/or CLI

  • Validate inputs against defined system constraints

  • Automatically compute:

    • Required number of modules

    • Interface bandwidth

    • Memory allocations

    • Control architecture

  • Generate:

    • Visual block diagrams

    • Documentation snippets

    • HDL module instantiations or configuration files

  • Export functionality:

    • Export the derived setup in a suitable manner

Name:

@Sai Bhavani

Thesis Type MA/BA/PA:

PA

Student ID / Matrikelnummer:

610995

Field of Study / Studiengang:

Microelectronics

Official start-date / Offizieller Beginn:

Apr 29, 2025

Final-report-due /Abgabe:

Aug 19, 2025

Spotlight-presentations:

  1. May 27, 2025

  2.  

Finale presentation / Abschlusspräsentation

 

Zweitprüfer / Second Examiner

@Moritz Hollenberg

Confidential / Vertraulich

No

Checklist

Helpful links:

Document Upload Final Thesis / Dokumentenabgabe Abschlussdokument

File of final presentation / Dokumentenabgabe Abschlusspräsentation

Link for further files / Link für weitere Dokumente

 

Institut für Mechatronik im Maschinenbau (iMEK), Eißendorfer Straße 38, 21073 Hamburg